When high energy particles such as alpha particles pass through semiconductor devices they can cause soft errors to occur. Soft errors are particularly problematic in memory devices such as DRAM and SRAM memory cells. When a high energy particle passes through a node of a memory cell that is storing charge (e.g., a DRAM or SRAM memory cell), if the energy of the particle is sufficiently strong or if the capacitance is too small, the node can be effectively discharged. This can reverse the stored logic state of the memory cell (e.g., the cell can be flipped from storing a logic “1” to a logic “0”). The resulting error is typically referred to as a “soft error.”
The issue of soft errors in memory cells has been studied in depth and many solutions have been developed for decreasing the soft error rate of memory cells. However, high energy particles can also cause soft errors in logic devices. The movement toward higher device densities and lower device voltages has led to a corresponding increase in likelihood for soft errors to occur in logic devices.
During the design of a semiconductor device, cells from a cell library are combined to form a design that performs the desired function. Though conventional standard cell libraries include numerous devices, some of which will have higher soft error rate than others, it is difficult to design logic that has high soft error resistance. More particularly, since the cells in standard cell libraries are typically designed for speed and not soft error resistance, the standard cell library may not include a particular type of logic device having the desired soft error resistance.
Accordingly, there is a need for a cell library that allows for easily forming designs having increased soft error resistance. Also, there is a need for a method and apparatus that reduce the occurrence of soft errors in logic devices. The method and apparatus of the present invention meets the above needs.